1. Field of the Invention
The invention relates to the field of solid state electronics. More particularly, the invention relates to a method of fabricating a semiconductor device and a device so formed.
2. Description of the Prior Art
Generally, semiconductor devices are manufactured by producing various layers of semiconductor material upon a silicon substrate. To facilitate structural support of the device and provide a conductive pad to connect a conductive lead, the device is typically attached by solder to a lead frame. The lead frame attaches only to a specific, centrally located portion of the device and the remainder of the device is electrically isolated from the lead frame by an air gap. During encapsulation of the device, this air gap is typically filled with an insulating material used to encapsulate the device. In this manner, the gap prevents edges of the device from inadvertently shorting to the lead frame, mitigates electrical arcing from the device to the lead frame and reduces possible device breakdown. Typically, such an air gap provides adequate electrical isolation of the edges of the semiconductor device from the lead frame. For many devices, the voltage difference between the edges of the device and the lead frame is zero volts, thus arcing cannot occur and shorting has no effect on device performance. Moreover, for other devices, the maximum voltage difference between the device edges and the lead frame is relatively small and the typical spacing used to provide isolation between the device edges and the lead frame provides sufficient isolation. However, in many high-voltage devices, the typical spacing may not be adequate to prevent arcing between the device edges and the lead frame. Therefore, in high voltage devices, electrical isolation of the edges of a device can be problematic.
In the past, the general practice for constructing a high-voltage semiconductor device has been to use a junction isolation structure within the device to provide electrical isolation of the edges of the device from the lead frame attached to the device. Typically, isolation for a typical junction is provided by diffusing into the edges of the device, a layer of impurities. This layer of impurities contains the same concentration of impurities as a bottom layer of the device, i.e., the layer that connects to the lead frame. In this manner, a uniformly doped semiconductor layer extends along the entire bottom of the device including where the device connects to the lead frame, and along vertical sides of the device. In short, this layer is formed wherever the device is closely spaced from the lead frame. Because the lead frame connects to this bottom layer, the lead frame and the bottom layer have the same potential. As such, there is no potential difference between the device edges and the lead frame to facilitate arcing or detrimental shorts and, therefore, this junction isolation structure achieves the desired electrical isolation. Although this isolation technique provides isolation for many device designs, the technique has not proved entirely satisfactory. For instance, in many devices, there is not sufficient space on the device to provide junction isolation for the sides of the device. In other devices, the device layout does not permit a uniformly doped layer to extend along its sides and bottom. Also, the added expense of providing junction isolation to a chip is usually substantial.
Consequently, those concerned with the development of high-voltage integrated circuits and other semiconductor devices have long recognized the need for improved fabrication techniques which provide electrical isolation of the device edges from its lead frame.